1. Field of the Invention
The present invention relates to a designing method for a large-scale integrated circuit such as a system LSI, etc., and more particularly, to a critical path estimating method for making a layout process efficient by excluding an exception path, which is estimated to be a critical path having a severe timing condition, among exception paths having no possibilities of being used in the operations of an actual circuit instead of making a timing analysis by targeting all of paths between arbitrary two memory elements within an integrated circuit in a static timing analysis.
2. Description of the Related Art
Generally, in a design of an integrated circuit such as a system LSI, first as a functional design from system specification, an operation description, for example, in C language is obtained, logic synthesis of a bottom-up technique for creating, by way of example, a net list as a description of a logic level, for example, is made, for example, via a register transfer level (RTL) description, and a layout design process as a determination of arrangement and wiring is executed thereafter.
In a layout design process, a static timing analysis (STA) for making timing verification by targeting all of paths between arbitrary two memory elements within an LSI is made in correspondence with an actual wire load. With the STA, the timing verification which targets all of paths between arbitrary two memory elements within an LSI is made. However, since the timing verification is made also for exception paths having no possibilities of being actually used within the circuit among the paths, the processing amount of the timing verification becomes enormous as the circuit scale of the LSI increases.
As one of file formats of various types of setting condition data for the timing verification, a synopsis design constraint (SDC) is widespread. In recent years, a tool for automatically extracting exception paths within an LSI has been used to shorten the turn around time (TAT) of LSI design. However, the number of exception paths extracted with such an SDC automatic generation tool tends to become enormous with an increase in the scale of a circuit.
Originally, the efficiency of a layout process significantly increases if the layout process can be executed by excluding exception paths extracted with such a tool. However, there are problems such that even a memory amount itself for storing the data of exception paths cannot be prepared when the scale of a circuit is large, and that a processing amount for excluding numerous exception paths from targets of the timing verification becomes enormous even if the data of exception paths can be stored in a memory, and extraction results of the SDC automatic generation tool cannot be used effectively. Accordingly, there is a conventional problem such that extraction results of the SDC automatic generation tool can be used only as a comparison material in the evaluation of critical paths in STA corresponding to a layout process even if exception paths are automatically extracted with such a tool, and this is not helpful for making a layout process efficient.
Additionally, as a conventional technique for using SDC, there is also a method for creating SDC by making STA based on a tentative wire load, for example, a wire load model (WLM) before a layout. This method, however, poses a problem that design processing procedures become cumbersome.
Japanese Patent Application Publication No. HEI6-215061, as such a conventional technique for extracting critical paths within an LSI, discloses a technique, which assumes a gate level simulation and extracts critical paths by targeting a simulation execution range interactively specified with GUI in an initial design stage of an LSI. Even this conventional technique cannot solve the problem such that handling of all of paths extracted, for example, with an SDC automatic generation tool as exception paths hinders a layout process from being efficient.